1. Field of the Invention
This invention relates to a Gilbert amplifier circuit, and more particularly is suitably applicable to a predrive circuit for-driving a cathode ray tube by an amplifier circuit operating in a wide frequency band and a gain control circuit using an amplifier circuit, and also applicable to an integrated circuit having low power consumption.
2. Description of the Related Art
In general, the input stage of a conventional Gilbert amplifier was composed of a grounded-emitter differential amplification stage, the differential output of which is converted into a collector current by a differential pair of the poststage and the change of a voltage across a load resistor R.sub.L1 is outputted.
For example, as shown in FIG. 1, the input stage 2 of a Gilbert amplifier 1 is composed of a differential pair consisting of transistors Q1 and Q2, the emitters of which are connected to each other through an input resistor R.sub.IN. Constant-current sources 4 and 5 are also connected to the emitters of transistors Q1 and Q2 respectively. This construction is generally used as an input stage 2.
A differential output is supplied to the bases of transistors Q5 and Q6 constituting a differential output stage 3 from transistors Q3 and Q4 which are cascade connected to the collectors of transistors Q1 and Q2, respectively.
Gain G of this Gilbert amplifier 1 can be obtained by the following equation: ##EQU1## where I.sub.0 is an emitter current of constant-current sources 4 and 5, which are connected to the differential pair of the input stage 2, I.sub.1 is an emitter current of the constant-current source 6, which is connected to the differential pair of the differential output stage 3, R.sub.IN is an input resistance and R.sub.L1 is a load resistor.
However, when the input signal V.sub.IN is inputted, an inphase input flows into inverted output, because there are a base contact resistance r.sub.b and a signal source impedance R.sub.S in the base of transistor Q1 and there also are a base-to-collector capacity C.sub.CB between the base and collector and a base-to-emitter capacity C.sub.BE between the base and the emitter, respectively. Therefore, it was not possible to extend the frequency characteristic of the output stage to a higher frequency.
That is, the high-range cut-off frequency f (-3 [dB]) in a Gilbert amplifier 1 is expressed using the following equation: ##EQU2## where an input impedance of transistor Q1 is r.sub.90, an emitter resistance is r.sub.e, and a mutual conductance is g.sub.m. It was impossible to extend the frequency characteristic to a higher frequency band because the denominator of the equation (2) increases due to the existence of various kinds of resistance and capacitance.
Also, emitter follower output stages in an integrated circuit are conventionally arranged as shown in FIGS. 2 and 3, to output an output signals V.sub.OUT from output pin P11 and P12 respectively.
Here, the output stage of an integrated circuit 10 (FIG. 2) is arranged to drive an NPN type transistor Q11 with an input signal V.sub.IN amplified by an operational amplifier AMP10, and output an output signal V.sub.OUT generated across a load resistance R11, which is connected to the emitter of the transistor Q11, from the output pin P11.
Also, the output of an integrated circuit 12 (FIG. 3) is arranged to constant-current-drive an NPN type transistor Q12 by connecting a current source 13 to the emitter of the transistor Q12, and to output an output signal V.sub.OUT from an output pin P12.
However, it is impossible to expand the frequency characteristics to a sufficiently high frequency range because the output stage of the integrated circuit has load capacitance C10 (or C11) such as capacitance of a pin (4-5 [pF]) or capacitance of external components, and the output stage must drive such load capacitance C10 (or C11) with the voltage output signal V.sub.OUT.
For example, in the case of the output stage of the integrated circuits 10 and 12, taking V.sub.P-P for amplitude of an output signal to be found, f.sub.max for the maximum value of the signal frequency, and t.sub.min for the settling time (wherein fmax.tmin=0.35), there is a following relationships: EQU .pi..fmax.VP-P=SR (3) ##EQU3## and also by using equations (3) and (4), the minimum output current I.sub.min for supplying the output stage, is obtained the following relationship: EQU I.sub.min =.pi..f.sub.max.V.sub.P-P.C1 (5)
That is, it can be recognized that much output current is required when it is desired to increase the output amplitude outputted from the integrated circuits 10 and 12, and when high frequency characteristics are required.
However, the greater the output current is, the more the base cumulative capacity of the NPN type transistor increases, or the current amplification factor h.sub.FE decreases in the high frequency band. As a result, the output impedance becomes higher and causes oscillation to occur easily. Therefore, it becomes necessary to connect a resistor to the base of the transistor Q1 to suppress this oscillation, and the frequency characteristics can be expanded only as high as 40 to 50 [MHz] with influence of resistance.
Then, it has been contemplated to arrange the output stage in a push-pull circuit to drive the load capacitance C20 (or C30) (FIGS. 4 and 5).
In the case of the output stage of an integrated circuit 20 (FIG. 4), the frequency characteristics can be expanded in comparison with integrated circuits 10 and 12. However, the frequency characteristics can only be expanded to about 150 [MHz] under the effect of the low transition frequency f.sub.T of a PNP type transistor Q22, which constitutes the push-pull circuit with the NPN type transistor Q21.
Also, in the case of the output stage of an integrated circuit 30 (FIG. 5), it is arranged to connect the NPN type transistors Q31 and Q33 in a series, and connect a buffer amplifier AMP31 and an inverting buffer amplifier AMP32 to the base of each transistor Q31 and Q33, respectively, to operate the output stage in the push-pull operation. However, the frequency characteristics cannot be expanded to a sufficiently high frequency range because of the difference in the delay time between the buffer amplifier AMP31 and the inverting buffer amplifier AMP32.
Then, as shown in FIG. 6, it has been contemplated to connect to the output of the inverting buffer amplifier AMP43 an auxiliary current generator circuit 47 which can add current I.sub.SPEED given by the following equation: ##EQU4## through a speed-up capacitor C.sub.SPEED only when an input signal at high frequency is inputted, to idling current I.sub.0, and cause it to flow.
This arrangement allows it to maintain the idling current which constantly flows through the output stage, at a constant value of I.sub.0 even when it is necessary that a signal in the high frequency range be amplified, or when a signal with large amplification is desired to be obtained so that it is possible to suppress the increase of cumulative capacity and to expand the frequency characteristics.
However, the capacity of the speed-up capacitor C.sub.SPEED of several [pF] may easily vary in its production process by several tens of a percent or more, and the gains of the buffer amplifier AMP31 and the inverse buffer amplifier AMP32 may also vary.
Therefore, there is such a shortcoming that the amplification V.sub.P-P of the inverted output outputted from the inverse buffer amplifier AMP43 also varies to vary the output current as well so that the frequency characteristics are caused to vary.
Also, conventionally, a two-stage, gain control amplifier circuit as shown in FIG. 7 is employed as an amplifier circuit capable of outputting, after amplification at a gain, various kinds of input wide-band analog signals such as an image pickup signal as output from an image pickup element.
A gain control amplifier circuit 50 consists of two amplifying stages 52 and 53 whose fundamental constitution is a Gilbert amplifier. This amplifier circuit 50 can provide a variable gain over a wide frequency range by adjusting gains of the input stage 52 (having a proportional gain characteristic) and the output stage 53 (having an inversely proportional characteristic).
The input stage 52 consists of differential amplifying stages 52A and 52B. The voltage difference of the output voltages of the former differential amplifying stage 52A is converted by the latter differential amplifying stage 52B to a difference in collector currents, and a differential output is produced in accordance with this differential current.
That is, the differential amplifying stage 52A increases or decreases a current i (=(V.sub.IN -E52)/R51) flowing through an input resistor R1 of a differential pair consisting of transistors Q51 and Q52 in accordance with the voltage difference between an input voltage V.sub.IN and a reference voltage E52, and increases or decreases the collector currents flowing through transistors Q53 and Q54 which are connected in cascade to the differential pair.
Further, the differential amplifying stage 52A provides a voltage difference between emitter voltages, which are caused by the above collector current difference, to transistors Q55 and Q56, which constitute a differential pair of the differential amplifying stage 52B, to thereby produce, at resistors R52 and R53, differential outputs which change in accordance with the collector currents that increase or decrease in accordance with the difference between the input voltage V.sub.IN and the reference voltage E2.
The gain of the input stage 52 can be adjusted by increasing or decreasing the current I52 flowing through the constant current source that is connected to the common emitters of the transistors Q55 and Q56.
On the other hand, in the output stage 53, the differential outputs of the differential amplifying stage 52B are supplied to the bases of transistors Q57 and Q58, which constitute a differential pair of a differential amplifying stage 53A, and collector currents flowing through the transistors Q57 and Q58 are increased or decreased in accordance with the current i52 flowing through an input resistor R54.
Constant current sources 57 are connected to the connection points of the collectors of the transistors Q57 and Q58 and the emitters of the transistors Q59 and Q60, respectively. Since constant currents I54 flow into the transistors Q57 and Q58, a pair of collector current of the transistors decrease, as the constant current I54 increases while their difference is maintained. As a result, differential outputs having a gain increased as much as this are provided to a latter amplifying stage 53B.
In the differential amplifying stage 53B, a collector current flowing through a load resistor R55 is increased or decreased in accordance with the above voltage difference, and an amplified output signal V.sub.OUT is produced with a gain G given by the following equation: ##EQU5##
However, in the above gain control amplifier circuit 50, the parasitic collector capacitance of the collectors of the transistors Q55, Q56 and Q62 generates three poles at frequencies corresponding to the respective resistors R52, R53 and R55 within the frequency characteristics, which deteriorate the frequency response. Thus, the amplifier circuit 50 is not suitable for use as a wide-band amplifier circuit.
Furthermore, having a large number of elements and current sources, the gain control amplifier circuit 50 of the above construction consumes much power. In addition, the long signal path causes a reduction of the S/N ratio.
In the monitor driving circuit used in the monitor, etc., to expand frequency characteristics of a gain control amplifier for amplifying and outputting each primary color signal (R, G, or B) with any gain G to a wide frequency band, it has been attempted to constitute the gain control amplifier, which amplifies each primary color image signal (R, G, or B) so as to reduce cross-talk between them, by a separate integrated circuit for each primary signal.
In such an approach, the integrated circuit corresponding to each primary color image signal (R, G, or B) can be designed in the same circuit board pattern so that it is easy to match the frequency characteristics for the three channels, and also advantageous in improving the frequency characteristics.
However, it is very difficult to match all of the gain control curves of the integrated circuit corresponding to each primary color image signal (R, G, or B) because of variations in resistance and current amplification h.sub.FE caused in the production process of semiconductors. Thus, they generally exhibit unmatched gain control characteristics as shown in FIG. 8.
It is especially difficult to match the gain characteristics near the minimum gain because there is discord between the three primary color image signals (R, G, and B).
As the gain control amplifier for the primary color image signals (R, G, and B), it is contemplated, for example, to use a Gilbert type gain control amplifier 70 which consists of two differential amplifying stages as shown in FIG. 9. However, in this case, there is a problem in that the linearity at the minimum and maximum gain is deteriorated.
Here, the first stage of the gain control amplifier 70 consists of a differential pair of transistors Q71 and Q72, each emitter of which is connected through an input resistance R.sub.IN, and each collector of which is connected to a diode D71 and D72, respectively. The difference between the base voltages applied to the transistors Q71 and Q72 is controlled by a control voltage V.sub.x so that the difference between the differential voltages V71 and V72 applied to the differential pair in the second stage is controlled.
By the way, each emitter of the transistors Q71 and Q72 is connected to a constant-current-source 72 which supplies constant current I.sub.0.
The second stage of the gain control circuit 70 consists of a differential pair of transistors Q73 and Q74 to the bases of which differential outputs V71 and V72 are inputted, respectively. Collector current flowing through a load resistance R.sub.L70 is arranged to be increased or decreased and outputted as an output signal V.sub.OUT by multiplying the collector current caused to flow by the difference voltage between the differential outputs V71 and V72 with signal current I.sub.S flowing through a current source 73 connected to a common emitter.
In this gain control circuit 70, because at the maximum or minimum gain, a collector current (2I.sub.0) corresponding to current flowing through the two current sources 72 flows through either one of the transistors Q71 or Q72 constituting the first stage, while little current flows through the other one, there is a problem that the effect due to the resistance r.sub.e between the base and the emitter noticeably deteriorates the linearity of gain control characteristics (FIG. 10).
Thus, it is difficult to match the gain of each primary color signal near the minimum gain because there arises a potential difference in the output signals corresponding to the primary color image signals (R, G, and B) and the inclinations of the characteristic curves fail to match.
Therefore, if it is intended to match the output voltage at the minimum gain, it is necessary to always maintain the value of input dynamic range R.sub.IN.I.sub.0 at a constant voltage, which in turn requires to control the accuracy of the power supply voltage value and the band gap voltage value.
In order to control the accuracy of the power supply voltage value and the band gap voltage value, it is sufficient to control the current flowing through the constant-current-sources 72 shown in FIG. 9 by a correction circuit 80 with a current mirror arrangement as shown in FIG. 11.
In this case, assuming a current flowing through bias resistors R91 and R92 to be i, and the base voltage of the transistor Q91 to be V.sub.a, relationships for the following equations are established regarding current I.sub.0 flowing through bias resistors R93 and R94: EQU V.sub.CC -4V.sub.BE =(R91+R92).i (8) EQU Va-3V.sub.BE =(R93+R94).I.sub.0 ( 9) EQU Va=4V.sub.BE +R92.i (10)
Therefore, the constant current 10 is given by the following equation: ##EQU6## where, if the resistance ratio between the resistors R91 and R92 is 3:1, the current I.sub.0 given by equation (11) is: ##EQU7##
This allows the input dynamic range R.sub.IN.I.sub.0 to have a constant voltage value if the power supply voltage V.sub.CC does not have thermal characteristics and the accuracy of voltage value is high because the thermal characteristics of the input resistance R.sub.IN are canceled by internal resistances R93 and R94 with the same thermal characteristics which are expressed by the following equation (13): ##EQU8##
However, because this control voltage V.sub.X is controlled by a microcomputer, it is required that the power supply voltage have the same power supply voltage of V.sub.CC as that of the power supply for the microcomputer, and that a power supply terminal separate from the main power supply V.sub.CC1 for the predriver integrated circuit be provided. Thus, there arises a problem in that the arrangement becomes complicated.
It may be contemplated to make the resistance r.sub.e between the base and the emitter to apparently disappear by feedback control of the emitter potential of the transistors Q81 and Q82 with a differential amplifier. However, in this case, there is a shortcoming in that at the maximum or minimum gain, the transistors Q81 and Q82 are cut off and easily oscillated.